The invention relates to an integrated circuit comprising a first and a second clock domain being respectively controlled by a first and a second clock signal, the first clock domain and the second clock domain being interconnected via a set of interface signal paths, each of which comprising a respective string of flip-flops, an initial flip-flop of the string being located in the first clock domain and a final flip-flop of the string being located in the second clock domain, the string being arranged for serially moving a data bit along its flip-flops from the first to the second clock domain under control of the first and the second clock signals. The invention also relates to a method of testing such a circuit.
A clock domain comprises a set of elements (e.g. flipflops and combinatory logic elements) and is under control of a single clock signal. A clock domain will often coincide with a core, i.e. a more or less independent functional unit. A chip design is then a combination of cores, possibly from different manufacturers. For a normal mode of the resulting integrated circuit, the precise cycle in which data is transferred from one core to another may not be critical as the design will normally allow a window of several cycles in which to capture the data. In a test mode, however, it is vital that every cycle is totally predictable. It can be imagined that it is a hard task to synchronize different cores, especially as the clock domains are at different locations on the chip, which introduces extra problems with respect to clock skew. Therefore, normally, clock domains have mutually different phases. Within a clock domain, special care is taken with regard to the distribution of the clock signal to the flipflops, so that there is minimal risk of clock skew.
The presence of interface signal paths between the first and the second clock domain poses problems when testing the circuit. While testing the second clock domain, the first clock domain will generate new data and propagate it via the interface signal paths to the second clock domain. The precise cycle in which data is transferred is unpredictable. Consequently, new data is generated in the second clock domain, interfering with the testing of the clock domains in an unpredictable manner.
The problem is of particular importance when the clock domains have a scan-based design for testability. A scan-based design is characterized in that the flip-flops of the circuit are scannable, meaning that, in addition to the set of normal data paths realizing the intended functionality of the circuit, a set of test data paths is provided, cascading the flip-flops to form scan chains. A scan chain is essentially a shift register that allows the flip-flops contained therein to be loaded and unloaded serially, in that way enabling the circuit to be tested according to the scan test principle.
The scan test principle works as follows. Firstly, the circuit is put to a scan state, during which test patterns are shifted into the scan chains. Secondly, the circuit is put to an execution state, during which the clock signals of the respective clock domains are made active for a single period, while the input signals of the circuit are held at pre-set values. Thus, response patterns are generated in the scan chains under influence of the loaded test patterns and input signals, and guided by the combinatory logic elements in the normal data paths of the circuit. Thirdly, after putting the circuit into the scan state again, the response patterns are shifted out from the scan chains for evaluation. This sequence can be repeated for a large number of test patterns and combinations of input signals. Faults result in response patterns deviating from response patterns that would result in the absence of faults.
However, the response patterns generated in the scan chains of the first clock domain can alter incoming interface signals to the second clock domain via the interface signal paths between them. Since the two clock signals will normally have mutually different phases, it is uncertain whether the flip-flops of the second clock domain react to the new or to the initial values of the outgoing interface signals, or even enter a metastability state. In this way, unpredictable response patterns are generated in the second clock domain. Moreover, the interface signal paths themselves can not be tested.
A solution to this problem is described in U.S. Pat. No. 5,008,618, owned by the assignee of the present invention. According to the known method, the clock domains are tested sequentially. The incoming interface signals to the clock domain under test will not change as only the clock signal of that clock domain is enabled while the others are disabled. A disadvantage of the prior art solution is that it requires extra circuitry in the clock lines, consequently limiting the speed of the circuit.